[[Category:Parts]] 6Maq5IyHSuc R_PbjbRaO2E HicV3Z6XLFA =References= * [[https://horizon-eda.org/|Horizon EDA]] 3lqr6CAOwH4 ======Semiconductor Fabrication====== * [[https://github.com/aolofsson/awesome-opensource-hardware|Github: Awesome Open Source Hardware]] * [[https://www.nature.com/articles/s41586-021-03625-w.pdf|A natively flexible 32-bit Arm microprocessor]] * https://www.youtube.com/user/szeloof/videos * http://sam.zeloof.xyz/first-ic/ * [[https://www.yokogawa.com/yjp/solutions/solutions/minimal-fab/]] * [[https://www.minimalfab.com/en/]] * [[https://theamphour.com/390-an-interview-with-sam-zeloof/]] RJXio_jpc_Y * Kirt R. Williams, Kishan Gupta, Matthew Wasilik - Etch Rates for Micromachining Processing—Part II * Mark R. Jackson - Effects of Radio Frequency Power and Sulfur Hexafluoride Flowrate on Etch Rate of Silicon Dioxide * S. A. Moshkalyov, C. Reyes-Betanzo, R.C. Teixeira, I. Doi, M.B. Zakia, J.A. Diniz, J. Swart - Etching of Polycrystalline Silicon in SF6 Containing Plasmas * I.J. Kima, H.K. Moona, J.H. Leea, N.E. Leea, J.W. Jungc, S.H. Cho - Silicon nitride etch characteristics in SF6/O2 and C3F6O/O2 plasmas and evaluation of their global warming effects * http://microchem.com/pdf/PMMA_Data_Sheet.pdf * http://ww2.che.ufl.edu/unit-ops-lab/experiments/semiconductors/semiconductors-index.htm * http://sam.zeloof.xyz/category/semiconductor/ * https://www.amazon.com/dp/0130224049/?coliid=I2YFXQKLTBAQQB&colid=2HIJ0SI208R11&psc=0&ref_=lv_ov_lig_dp_it?tag=replimat-20 * [[https://mycroft.ai/|Mycroft open source voice assistant]] * [[https://www.kickstarter.com/projects/opencv/opencv-ai-kit/|OpenCV kit]] * [[https://en.wikipedia.org/wiki/Industrial_control_system|Wikipedia: Industrial control system]] * [[https://www.nature.com/articles/s41586-021-03544-w.epdf?sharing_token=8za_nMkuk42509LyAn-xY9RgN0jAjWel9jnR3ZoTv0PW0K0NmVrRsFPaMa9Y5We97spjdO-aPpvZYXPHhKbfpfPljZaIm3b-kyQ3gKElVBjZIxn_5lBKsnqIIUn2YkCI3IFe5puGE49yIrhVbJrW9eUbKmMo7FS9KDgM4hs9TFFEBv1CLtLi4EFaXPirF-G_lwtOzFcc-pVSzW5vcQBQt19OPe2Fx4nUQHU5ItFuNC8%3D|A graph placement methodology for fast chip design]] XVoldtNpIzI IS5ycm7VfXg